Kevin La Ra

Summary

I am a systems and compute engineer focused on the infrastructure that enables modern artificial intelligence. My interests include GPU architectures, high-performance computing, and hardware/software co-design. I am currently pursuing a master’s degree in Computer Engineering at Arizona State University, where my coursework emphasizes advanced computer architecture, operating systems, and reconfigurable computing for AI workloads.

My background spans semiconductor design and validation, embedded software systems, large-scale aerospace platforms, and systems engineering roles across companies including Intel, Northrop Grumman, Boeing, Garmin, and Microchip Technology. I bring more than 15 years of experience developing in C/C++ and Python for embedded and physical systems, complimented with executive leadership training from Stanford and systems engineering from MIT.

Earlier in my career, I served as a U.S. Navy officer, an experience that shaped my approach to technical leadership, disciplined execution, and operating complex systems under real-world constraints.

Core Technical Areas

• AI & Accelerated Computing Systems (GPUs, SoCs, FPGA platforms)
• Embedded & Real-Time Software (ARM, RTOS, avionics)
• Computer Architecture
• Hardware/Software Co-Design
• System-On-Chip (SoC) Validation (Unit and Full-Chip Testing)
• Silicon Bring-Up (Power-on, DFT, SCAN)
• Real-Time & Safety-Critical Software
• FPGA-Based Emulation
• Systems Architecture & Requirements Engineering
• Technical Program Leadership
• Agile Technical Leadership (Scrum Master, Product Owner)
• Defense & Aerospace Systems

Selected Industry Experience

Microchip Technology — Embedded Verification Engineer / Project Lead

• Led verification of an ARM Cortex-M33 microcontroller prior to tape-out on a multinational engineering team.
• Developed C-based verification suites and executed hardware emulation using Xilinx FPGA platforms.
• Updated peripheral drivers to streamline product configuration and eliminate manual register workflows.
• Served as emulation lead for next-generation MCU program, owning schedule, execution tracking, and cross-site reporting.

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Intel — Hardware Design & Validation Engineer

• Led first-silicon validation and debug of IOP331 processor, including architecture bring-up and performance characterization.
• Designed VHDL-based test logic and authored Design-for-Test architecture specifications.
• Contributed to PCI-X bus controller development for datacenter RAID ASICs.
• Coordinated multi-site validation efforts across 10 engineers and three locations.

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Northrop Grumman — Senior Principal Engineer (Software & Systems)

• Deputy software lead for large-scale missile interceptor programs, overseeing flight-software modernization and embedded OS upgrades.
• Led integration of new IMU-based guidance systems, establishing test benches, verification plans, and cross-disciplinary delivery schedules.
• Served as requirements thread lead on the Sentinel ICBM program, defining verification strategies and system decomposition with U.S. Air Force stakeholders.
• Championed Agile adoption and acted as Scrum Master across a 30-engineer organization.

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Garmin — Aviation Software Engineer

• Led development of touchscreen control systems and electronic circuit breaker software for Bell 525 helicopter avionics.
• Built embedded C software for G5000 glass-cockpit platforms across multiple business jet aircraft.
• Authored verification test suites compliant with DO-178B safety standards.

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United States Navy — Cryptologic Officer

• Directed training, evaluation, and operational execution for 35 intelligence analysts supporting Pacific-region missions.
• Selected for the Navy Nuclear Propulsion Officer Candidate (NUPOC) program.

Education

Leadership and Service

Selected Technical Areas

Certification / Clearances